Jason Lau - An FPGA HLS Researcher

We propose a robust Design Space Exploration (DSE) framework to address the instability and manual complexity of existing High-Level Physical Synthesis (HLPS) for multi-die FPGAs. By automating iterative parameter tuning through physical implementation metrics and tailored heuristics, our framework ensures consistent timing closure and eliminates user intervention. In evaluations on large-scale designs, the framework achieved an average frequency of 311.06 MHz, outperforming the AMD Vitis/Vivado toolchain by 2.42× and leading academic solutions by 1.67×.

We present the concept of high-level physical synthesis (HLPS), and a practical infrastructure for representing the composition of complex FPGA designs and exploring physical optimizations. Our approach introduces a flexible intermediate representation that captures interconnection protocols at arbitrary hierarchical levels, coarse-grained pipelining, and spatial information, enabling the creation of reusable passes for design frequency optimizations. RapidStream IR improves the frequency of a broad set of mixed-source designs by 7% to 62%.

We propose CHARM, a framework designed to optimize throughput for end-to-end deep learning applications on the AMD/Xilinx Versal ACAP. To overcome the performance bottlenecks caused by executing small matrix multiply (MM) layers on monolithic accelerators, CHARM composes multiple diverse, concurrent accelerator architectures tailored to varied layer sizes. By utilizing analytical models for design space exploration and automated code generation, CHARM achieves throughput gains of up to 32.51x over monolithic designs across models like BERT and ViT.

We introduce Heterosys, an end-to-end framework designed to bridge the gap between high-level software and efficient FPGA implementation. By decoupling algorithmic descriptions from underlying hardware, Heterosys utilizes three core components—HeteroRefactor for automated refactoring and selective offloading, Adroit for frequency-driven architectural optimization, and RapidIR for high-level physical synthesis and floorplanning. Our research demonstrates frequency improvements of 30% to over 100%, resource reductions up to 90%, and a 51% decrease in manual code effort, significantly lowering the barrier to entry for heterogeneous computing.

We propose TAPA, an end-to-end framework for compiling C++ task-parallel programs into high-frequency FPGA accelerators. By utilizing flexible communication APIs and coarse-grained floorplanning during compilation, TAPA enables accurate pipelining of critical paths and optimizes designs for HBM-based FPGAs. Experimental results across 43 designs demonstrate a 102% average frequency improvement, including successful implementation of previously unroutable designs with minimal resource impact.

We present RapidStream, a parallelized, physical-integrated compilation framework designed to drastically reduce FPGA compilation cycles. By co-optimizing HLS with back-end physical implementation, RapidStream partitions latency-insensitive C/C++ programs for parallel placement and routing. RapidStream achieves a 5–7× reduction in compile time and up to a 1.3× increase in frequency compared to commercial toolchains.

We propose CHARM, a framework for composing heterogeneous matrix multiply (MM) accelerators to optimize deep learning throughput on platforms like the AMD/Xilinx Versal ACAP. While monolithic accelerators struggle with the small, diverse MM layers found in models like BERT—often achieving less than 5% peak performance—CHARM utilizes analytical models to partition resources and schedule layers across multiple concurrent, specialized architectures. By automating code generation and design space exploration, CHARM achieves up to 32.5x throughput gains over monolithic designs across BERT, ViT, NCF, and MLP benchmarks.

We evaluate the decade-long evolution of FPGA HLS from prototype to industrial deployment across domains like deep learning and genomics. While highlighting HLS successes, we identify critical bottlenecks in clock frequency, system integration, and code legacy, proposing a roadmap for future research centered on open-source infrastructures and standardization.

We present Sextans, a flexible FPGA accelerator for general-purpose SpMM that addresses challenges in random memory access, data movement, and workload balancing. By leveraging HBM and PE-aware scheduling, Sextans enables streaming access and balanced pipelining for arbitrary matrix sizes. Evaluation on 1,400 benchmarks shows that Sextans achieves up to a 2.50x speedup over K80 GPUs, with projected optimizations outperforming V100 GPUs.

We present TARO, an automated framework for applying free-running optimization to HLS-based streaming applications. By regulating tasks via data streams rather than complex global control, TARO simplifies hardware logic while preserving original functionality and performance. On the Alveo U250, TARO achieves an average reduction of 16% in LUTs and 45% in FFs for systolic array designs.

We introduce AutoBridge, an automated framework that closes the frequency gap between HLS-generated and handcrafted RTL designs by integrating coarse-grained floorplanning with pipelining during HLS compilation. By providing global layout awareness, AutoBridge identifies and pipelines long interconnects—particularly die-crossing wires in multi-die FPGAs—while preventing routing congestion. Across 43 configurations, AutoBridge increased average frequency from 147 MHz to 297 MHz (102% improvement) and successfully routed previously unroutable designs with negligible resource overhead and zero throughput loss.

We present TAPA, an automated HLS framework designed to enhance the productivity of task-parallel FPGA accelerators. While traditional HLS struggles with the complexities of parallel task communication and slow development cycles, TAPA introduces a programmer-friendly C++ interface, unconstrained software simulation, and fast hierarchical code generation. By streamlining the development and verification process, TAPA reduces kernel and host code by 22% and 51% respectively, while accelerating correctness verification by 3.2× and QoR tuning by 6.8×.

We propose HeteroRefactor, an automated refactoring framework that enables HLS for traditionally incompatible C/C++ programs containing recursion and dynamic memory. By monitoring FPGA-specific dynamic invariants—such as variable bitwidths and data structure sizes—HeteroRefactor automatically transforms kernels into synthesizable, resource-optimized hardware while using selective CPU offloading to ensure correctness. On Xilinx FPGAs, HeteroRefactor reduces BRAM usage by up to 83% and improves clock frequency by 42%, eliminating the need for extensive manual code refactoring by hardware experts.

We present a study on frequency degradation in HLS-generated FPGA designs, identifying broadcast structures—specifically high-fanout data, flow control, and synchronization signals—as the primary bottlenecks. By addressing HLS compiler limitations through broadcast-aware scheduling, synchronization pruning, and skid-buffer integration, our approach improves the maximum frequency of representative benchmarks by 53% on average, with gains exceeding 100 MHz in several cases.

We present a high-performance acceleration framework for chaining, the primary bottleneck in genome sequencing that accounts for 70% of execution time. By reordering operation sequences for hardware-friendly parallelism and implementing a fine-grained task dispatching scheme, we overcome the limitations of variable input sizes and poor data dependency. Our fully pipelined streaming architecture on FPGA achieves a 28x speedup over the highly-optimized multi-threaded CPU program and 4x over a fully-utilized GPU, providing a quantitative guide for selecting optimal hardware platforms for genomic workloads.

We present an evaluation of the Tersoff potential's performance portability on Intel Skylake and NVIDIA Volta architectures. While the original study claimed high efficiency and scalability through reduced precision and cross-platform vectorization, our experiments with updated datasets show inconsistent results. Analysis reveals that communication bottlenecks, triggered by specific characteristics of the new input data, significantly limit the reproducibility of the original performance gains.